--------------------------------------------------------------------------------
-- Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 11.1
--  \   \         Application : sch2hdl
--  /   /         Filename : schema.vhf
-- /___/   /\     Timestamp : 06/14/2010 22:55:18
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: sch2hdl -intstyle ise -family spartan3e -flat -suppress -vhdl C:/xilinks/Pokus2/schema.vhf -w C:/xilinks/Pokus2/schema.sch
--Design Name: schema
--Device: spartan3e
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesized and simulated, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity NAND6_MXILINX_schema is
   port ( I0 : in    std_logic; 
          I1 : in    std_logic; 
          I2 : in    std_logic; 
          I3 : in    std_logic; 
          I4 : in    std_logic; 
          I5 : in    std_logic; 
          O  : out   std_logic);
end NAND6_MXILINX_schema;

architecture BEHAVIORAL of NAND6_MXILINX_schema is
   attribute BOX_TYPE   : string ;
   attribute RLOC       : string ;
   signal dummy   : std_logic;
   signal I35     : std_logic;
   signal O_DUMMY : std_logic;
   component FMAP
      port ( I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             I4 : in    std_logic; 
             O  : in    std_logic);
   end component;
   attribute BOX_TYPE of FMAP : component is "BLACK_BOX";
   
   component AND3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
   
   component NAND4
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of NAND4 : component is "BLACK_BOX";
   
   attribute RLOC of I_36_96 : label is "X0Y0";
   attribute RLOC of I_36_97 : label is "X0Y0";
begin
   O <= O_DUMMY;
   I_36_96 : FMAP
      port map (I1=>I0,
                I2=>I1,
                I3=>I2,
                I4=>I35,
                O=>O_DUMMY);
   
   I_36_97 : FMAP
      port map (I1=>I3,
                I2=>I4,
                I3=>I5,
                I4=>dummy,
                O=>I35);
   
   I_36_98 : AND3
      port map (I0=>I3,
                I1=>I4,
                I2=>I5,
                O=>I35);
   
   I_36_105 : NAND4
      port map (I0=>I0,
                I1=>I1,
                I2=>I2,
                I3=>I35,
                O=>O_DUMMY);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity D147D_MUSER_schema is
   port ( A   : in    std_logic; 
          B   : in    std_logic; 
          C   : in    std_logic; 
          D   : in    std_logic; 
          LT  : in    std_logic; 
          RBI : in    std_logic; 
          Qa  : out   std_logic; 
          Qb  : out   std_logic; 
          Qc  : out   std_logic; 
          Qd  : out   std_logic; 
          Qe  : out   std_logic; 
          Qf  : out   std_logic; 
          Qg  : out   std_logic);
end D147D_MUSER_schema;

architecture BEHAVIORAL of D147D_MUSER_schema is
   attribute BOX_TYPE   : string ;
   attribute HU_SET     : string ;
   signal XLXN_3   : std_logic;
   signal XLXN_5   : std_logic;
   signal XLXN_20  : std_logic;
   signal XLXN_74  : std_logic;
   signal XLXN_75  : std_logic;
   signal XLXN_76  : std_logic;
   signal XLXN_78  : std_logic;
   signal XLXN_79  : std_logic;
   signal XLXN_80  : std_logic;
   signal XLXN_81  : std_logic;
   signal XLXN_82  : std_logic;
   signal XLXN_85  : std_logic;
   signal XLXN_86  : std_logic;
   signal XLXN_87  : std_logic;
   signal XLXN_89  : std_logic;
   signal XLXN_90  : std_logic;
   signal XLXN_91  : std_logic;
   signal XLXN_92  : std_logic;
   signal XLXN_96  : std_logic;
   signal XLXN_97  : std_logic;
   signal XLXN_104 : std_logic;
   signal XLXN_122 : std_logic;
   signal XLXN_130 : std_logic;
   signal XLXN_139 : std_logic;
   signal XLXN_150 : std_logic;
   signal XLXN_154 : std_logic;
   signal XLXN_155 : std_logic;
   component NAND2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of NAND2 : component is "BLACK_BOX";
   
   component INV
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of INV : component is "BLACK_BOX";
   
   component NAND6_MXILINX_schema
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             I4 : in    std_logic; 
             I5 : in    std_logic; 
             O  : out   std_logic);
   end component;
   
   component AND2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
   
   component AND3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
   
   component AND4
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             I3 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND4 : component is "BLACK_BOX";
   
   component OR3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR3 : component is "BLACK_BOX";
   
   component OR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
   
   attribute HU_SET of XLXI_5 : label is "XLXI_5_0";
begin
   XLXI_1 : NAND2
      port map (I0=>LT,
                I1=>A,
                O=>XLXN_5);
   
   XLXI_2 : NAND2
      port map (I0=>LT,
                I1=>B,
                O=>XLXN_130);
   
   XLXI_3 : NAND2
      port map (I0=>LT,
                I1=>C,
                O=>XLXN_150);
   
   XLXI_4 : INV
      port map (I=>D,
                O=>XLXN_155);
   
   XLXI_5 : NAND6_MXILINX_schema
      port map (I0=>XLXN_5,
                I1=>XLXN_130,
                I2=>XLXN_150,
                I3=>XLXN_155,
                I4=>XLXN_3,
                I5=>LT,
                O=>XLXN_20);
   
   XLXI_16 : INV
      port map (I=>RBI,
                O=>XLXN_3);
   
   XLXI_17 : NAND2
      port map (I0=>XLXN_20,
                I1=>XLXN_5,
                O=>XLXN_104);
   
   XLXI_18 : NAND2
      port map (I0=>XLXN_20,
                I1=>XLXN_130,
                O=>XLXN_122);
   
   XLXI_19 : NAND2
      port map (I0=>XLXN_20,
                I1=>XLXN_150,
                O=>XLXN_139);
   
   XLXI_20 : NAND2
      port map (I0=>XLXN_20,
                I1=>XLXN_155,
                O=>XLXN_154);
   
   XLXI_25 : AND2
      port map (I0=>XLXN_154,
                I1=>XLXN_122,
                O=>XLXN_75);
   
   XLXI_26 : AND3
      port map (I0=>XLXN_139,
                I1=>XLXN_130,
                I2=>XLXN_5,
                O=>XLXN_74);
   
   XLXI_27 : AND4
      port map (I0=>XLXN_155,
                I1=>XLXN_150,
                I2=>XLXN_130,
                I3=>XLXN_104,
                O=>XLXN_76);
   
   XLXI_67 : AND2
      port map (I0=>XLXN_154,
                I1=>XLXN_122,
                O=>XLXN_79);
   
   XLXI_68 : AND3
      port map (I0=>XLXN_139,
                I1=>XLXN_130,
                I2=>XLXN_104,
                O=>XLXN_78);
   
   XLXI_70 : AND2
      port map (I0=>XLXN_154,
                I1=>XLXN_139,
                O=>XLXN_81);
   
   XLXI_71 : AND3
      port map (I0=>XLXN_150,
                I1=>XLXN_122,
                I2=>XLXN_5,
                O=>XLXN_82);
   
   XLXI_72 : AND4
      port map (I0=>XLXN_155,
                I1=>XLXN_150,
                I2=>XLXN_130,
                I3=>XLXN_104,
                O=>XLXN_85);
   
   XLXI_73 : AND3
      port map (I0=>XLXN_139,
                I1=>XLXN_130,
                I2=>XLXN_5,
                O=>XLXN_86);
   
   XLXI_74 : AND3
      port map (I0=>XLXN_139,
                I1=>XLXN_122,
                I2=>XLXN_104,
                O=>XLXN_87);
   
   XLXI_76 : AND2
      port map (I0=>XLXN_139,
                I1=>XLXN_130,
                O=>XLXN_89);
   
   XLXI_77 : AND2
      port map (I0=>XLXN_122,
                I1=>XLXN_104,
                O=>XLXN_90);
   
   XLXI_78 : AND2
      port map (I0=>XLXN_150,
                I1=>XLXN_122,
                O=>XLXN_91);
   
   XLXI_79 : AND3
      port map (I0=>XLXN_155,
                I1=>XLXN_150,
                I2=>XLXN_104,
                O=>XLXN_92);
   
   XLXI_80 : AND3
      port map (I0=>XLXN_139,
                I1=>XLXN_122,
                I2=>XLXN_104,
                O=>XLXN_96);
   
   XLXI_81 : AND4
      port map (I0=>LT,
                I1=>XLXN_155,
                I2=>XLXN_150,
                I3=>XLXN_130,
                O=>XLXN_97);
   
   XLXI_118 : OR3
      port map (I0=>XLXN_76,
                I1=>XLXN_74,
                I2=>XLXN_75,
                O=>Qa);
   
   XLXI_119 : OR3
      port map (I0=>XLXN_80,
                I1=>XLXN_78,
                I2=>XLXN_79,
                O=>Qb);
   
   XLXI_120 : OR2
      port map (I0=>XLXN_82,
                I1=>XLXN_81,
                O=>Qc);
   
   XLXI_121 : OR3
      port map (I0=>XLXN_87,
                I1=>XLXN_86,
                I2=>XLXN_85,
                O=>Qd);
   
   XLXI_122 : OR2
      port map (I0=>XLXN_89,
                I1=>XLXN_104,
                O=>Qe);
   
   XLXI_123 : OR3
      port map (I0=>XLXN_92,
                I1=>XLXN_91,
                I2=>XLXN_90,
                O=>Qf);
   
   XLXI_124 : OR2
      port map (I0=>XLXN_97,
                I1=>XLXN_96,
                O=>Qg);
   
   XLXI_139 : AND3
      port map (I0=>XLXN_139,
                I1=>XLXN_122,
                I2=>XLXN_5,
                O=>XLXN_80);
   
end BEHAVIORAL;



library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity schema is
   port ( btn_0   : in    std_logic; 
          btn_1   : in    std_logic; 
          clk_1Hz : in    std_logic; 
          sw_0    : in    std_logic; 
          sw_1    : in    std_logic; 
          sw_2    : in    std_logic; 
          sw_3    : in    std_logic; 
          an_0    : out   std_logic; 
          an_1    : out   std_logic; 
          an_2    : out   std_logic; 
          an_3    : out   std_logic; 
          ca      : out   std_logic; 
          cb      : out   std_logic; 
          cc      : out   std_logic; 
          cd      : out   std_logic; 
          ce      : out   std_logic; 
          cf      : out   std_logic; 
          cg      : out   std_logic; 
          dp      : out   std_logic; 
          ld_0    : out   std_logic; 
          ld_1    : out   std_logic; 
          ld_2    : out   std_logic; 
          ld_6    : out   std_logic; 
          ld_7    : out   std_logic);
end schema;

architecture BEHAVIORAL of schema is
   attribute INIT       : string ;
   attribute BOX_TYPE   : string ;
   signal XLXN_25    : std_logic;
   signal XLXN_28    : std_logic;
   signal XLXN_29    : std_logic;
   signal XLXN_30    : std_logic;
   signal XLXN_31    : std_logic;
   signal XLXN_32    : std_logic;
   signal XLXN_33    : std_logic;
   signal XLXN_34    : std_logic;
   signal XLXN_35    : std_logic;
   signal XLXN_36    : std_logic;
   signal XLXN_37    : std_logic;
   signal ld_0_DUMMY : std_logic;
   signal ld_1_DUMMY : std_logic;
   signal ld_2_DUMMY : std_logic;
   component FD
      -- synopsys translate_off
      generic( INIT : bit :=  '0');
      -- synopsys translate_on
      port ( C : in    std_logic; 
             D : in    std_logic; 
             Q : out   std_logic);
   end component;
   attribute INIT of FD : component is "0";
   attribute BOX_TYPE of FD : component is "BLACK_BOX";
   
   component BUF
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of BUF : component is "BLACK_BOX";
   
   component PULLDOWN
      port ( O : out   std_logic);
   end component;
   attribute BOX_TYPE of PULLDOWN : component is "BLACK_BOX";
   
   component PULLUP
      port ( O : out   std_logic);
   end component;
   attribute BOX_TYPE of PULLUP : component is "BLACK_BOX";
   
   component D147D_MUSER_schema
      port ( A   : in    std_logic; 
             B   : in    std_logic; 
             C   : in    std_logic; 
             D   : in    std_logic; 
             LT  : in    std_logic; 
             RBI : in    std_logic; 
             Qa  : out   std_logic; 
             Qb  : out   std_logic; 
             Qc  : out   std_logic; 
             Qd  : out   std_logic; 
             Qe  : out   std_logic; 
             Qf  : out   std_logic; 
             Qg  : out   std_logic);
   end component;
   
   component AND3B2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3B2 : component is "BLACK_BOX";
   
   component AND3B3
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             I2 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND3B3 : component is "BLACK_BOX";
   
   component OR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of OR2 : component is "BLACK_BOX";
   
begin
   ld_0 <= ld_0_DUMMY;
   ld_1 <= ld_1_DUMMY;
   ld_2 <= ld_2_DUMMY;
   XLXI_21 : FD
      port map (C=>clk_1Hz,
                D=>XLXN_29,
                Q=>ld_2_DUMMY);
   
   XLXI_22 : FD
      port map (C=>clk_1Hz,
                D=>XLXN_30,
                Q=>ld_1_DUMMY);
   
   XLXI_23 : FD
      port map (C=>clk_1Hz,
                D=>XLXN_31,
                Q=>ld_0_DUMMY);
   
   XLXI_26 : BUF
      port map (I=>clk_1Hz,
                O=>ld_6);
   
   XLXI_27 : BUF
      port map (I=>btn_0,
                O=>ld_7);
   
   XLXI_29 : PULLDOWN
      port map (O=>XLXN_25);
   
   XLXI_30 : PULLUP
      port map (O=>XLXN_28);
   
   XLXI_31 : BUF
      port map (I=>sw_0,
                O=>an_3);
   
   XLXI_32 : BUF
      port map (I=>sw_1,
                O=>an_2);
   
   XLXI_33 : BUF
      port map (I=>sw_2,
                O=>an_1);
   
   XLXI_34 : BUF
      port map (I=>sw_3,
                O=>an_0);
   
   XLXI_35 : BUF
      port map (I=>btn_1,
                O=>dp);
   
   XLXI_36 : D147D_MUSER_schema
      port map (A=>ld_0_DUMMY,
                B=>ld_1_DUMMY,
                C=>ld_2_DUMMY,
                D=>XLXN_25,
                LT=>XLXN_28,
                RBI=>XLXN_28,
                Qa=>ca,
                Qb=>cb,
                Qc=>cc,
                Qd=>cd,
                Qe=>ce,
                Qf=>cf,
                Qg=>cg);
   
   XLXI_37 : AND3B2
      port map (I0=>btn_0,
                I1=>ld_0_DUMMY,
                I2=>ld_2_DUMMY,
                O=>XLXN_36);
   
   XLXI_38 : AND3B2
      port map (I0=>btn_0,
                I1=>ld_2_DUMMY,
                I2=>ld_1_DUMMY,
                O=>XLXN_37);
   
   XLXI_40 : AND3B2
      port map (I0=>btn_0,
                I1=>ld_0_DUMMY,
                I2=>ld_1_DUMMY,
                O=>XLXN_34);
   
   XLXI_41 : AND3B3
      port map (I0=>btn_0,
                I1=>ld_1_DUMMY,
                I2=>ld_0_DUMMY,
                O=>XLXN_32);
   
   XLXI_43 : OR2
      port map (I0=>XLXN_36,
                I1=>XLXN_37,
                O=>XLXN_29);
   
   XLXI_44 : OR2
      port map (I0=>XLXN_35,
                I1=>XLXN_34,
                O=>XLXN_30);
   
   XLXI_45 : OR2
      port map (I0=>XLXN_32,
                I1=>XLXN_33,
                O=>XLXN_31);
   
   XLXI_46 : AND3B2
      port map (I0=>btn_0,
                I1=>ld_0_DUMMY,
                I2=>ld_2_DUMMY,
                O=>XLXN_33);
   
   XLXI_47 : AND3B2
      port map (I0=>btn_0,
                I1=>ld_2_DUMMY,
                I2=>ld_0_DUMMY,
                O=>XLXN_35);
   
end BEHAVIORAL;


